Project Statistics |
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PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_performance_with_iobpacking.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2023-05-03T19:40:33 |
PROP_intWbtProjectID=F34193574AAB4FE103922D31F78482A0 |
PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xstNetlistHierarchy=Rebuilt |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_DevDevice=xc3s400 |
PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=pq208 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=20 |