| Program | | All Implementation Messages - Errors, Warnings, and Infos | New |
| xst | WARNING | HDLCompilers:299 - "Audio.v" line 279 Too many digits specified in binary constant | |
| xst | WARNING | Xst:905 - "Paula.v" line 660: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<ninebit> | |
| xst | WARNING | Xst:905 - "Floppy.v" line 360: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<reset> | |
| xst | WARNING | Xst:905 - "Minimig1.v" line 1055: One or more signals are missing in the sensitivity list of always block. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<ecs> | |
| xst | WARNING | Xst:647 - Input <scanline<1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <lbfdo<17:15>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1305 - Output <_dbg> is never assigned. Tied to value 000000. | |
| xst | WARNING | Xst:646 - Signal <rd_ack> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <l_dtack> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <addr_latch> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <_dbg_rd> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <data_in<15:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <mode<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <cnt> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <_boot> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1780 - Signal <step4> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1780 - Signal <step3> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1780 - Signal <step2> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <vpos<10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <volcntrld> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:643 - "Audio.v" line 456: The result of a 14x14-bit multiplication is partially used. Only the 14 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior. | |
| xst | WARNING | Xst:646 - Signal <scaledin<33:32>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <scaledin<15:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1780 - Signal <lfsr_reg> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <test_data<9:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:647 - Input <test_data<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:647 - Input <bplcon2<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:647 - Input <data_in<6:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:1305 - Output <sram_data_in> is never assigned. Tied to value 0000000000000000. | |
| xst | WARNING | Xst:1781 - Signal <rom_version> is used but never assigned. Tied to default value. | |
| xst | WARNING | Xst:646 - Signal <magic_size<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <bus_req_d> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <_l_addr<31:24>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <_l_addr<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <regporta<5:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <address_in<23:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:647 - Input <address_in<11:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:647 - Input <address_in<1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <bpu<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:737 - Found 8-bit latch for signal <reg_address_out>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. | |
| xst | WARNING | Xst:646 - Signal <shifted_old<35:32>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <shifted_new<35:32>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1780 - Signal <dumpcounter> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1780 - Signal <accuright> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1780 - Signal <acculeft> is never used or assigned. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <hpos<8:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:647 - Input <hpos<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <attach6> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <attach4> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <attach2> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <attach0> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <leda> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <osd_enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:647 - Input <cck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. | |
| xst | WARNING | Xst:646 - Signal <bplcon3<15:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <bplcon3<4:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <bplcon2<15:7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <bltcon1<11:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <xbs> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <sel_cia> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <gayle_nrdy> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <floppy_config<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <eclk<9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <eclk<7:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <dtr> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <cpu_speed> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <_dbg> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:646 - Signal <_cool_debug_wire> is assigned but never used. This unconnected signal will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1426 - The value init of the FF/Latch aron hinder the constant cleaning in the block CART1.
You should achieve better results by setting this init to 1. | |
| xst | WARNING | Xst:1710 - FF/Latch <wr_fifo_status_12> (without init value) has a constant value of 0 in block <pf1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1293 - FF/Latch <icr_4> has a constant value of 0 in block <cnt>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1293 - FF/Latch <icr_3> has a constant value of 0 in block <cnt>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <porta_in2_3> (without init value) has a constant value of 0 in block <CIAB1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <porta_in2_5> (without init value) has a constant value of 0 in block <CIAB1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1293 - FF/Latch <aron> has a constant value of 0 in block <CART1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <int7> (without init value) has a constant value of 0 in block <CART1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <l_int7_req> (without init value) has a constant value of 0 in block <CART1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <ram_ovl> (without init value) has a constant value of 0 in block <CART1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <mode_1> (without init value) has a constant value of 1 in block <CART1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <l_int7> (without init value) has a constant value of 0 in block <CART1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_0> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_24> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_25> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_26> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_27> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_28> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_29> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_30> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_31> of sequential type is unconnected in block <MIA1>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_0> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_1> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_2> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_3> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_4> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_5> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_6> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_7> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_8> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_9> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_10> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_11> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_12> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_13> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_14> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_15> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_32> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_33> of sequential type is unconnected in block <leftdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_0> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_1> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_2> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_3> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_4> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_5> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_6> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_7> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_8> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_9> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_10> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_11> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_12> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_13> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_14> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_15> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_32> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_33> of sequential type is unconnected in block <rightdac>. | |
| xst | WARNING | Xst:2677 - Node <scanline_1> of sequential type is unconnected in block <osd1>. | |
| xst | WARNING | Xst:2677 - Node <floppy_config_1> of sequential type is unconnected in block <osd1>. | |
| xst | WARNING | Xst:2677 - Node <t_chipset_config_0> of sequential type is unconnected in block <osd1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_7> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_8> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_9> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_10> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_11> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_12> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_13> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_14> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_15> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_0> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_1> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_2> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_3> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_4> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_6> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_7> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_8> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_9> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_10> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_11> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_12> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_13> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_14> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_15> of sequential type is unconnected in block <DENISE1>. | |
| xst | WARNING | Xst:2677 - Node <lbfdo_15> of sequential type is unconnected in block <AMBER1>. | |
| xst | WARNING | Xst:2677 - Node <lbfdo_16> of sequential type is unconnected in block <AMBER1>. | |
| xst | WARNING | Xst:2677 - Node <lbfdo_17> of sequential type is unconnected in block <AMBER1>. | |
| xst | WARNING | Xst:2677 - Node <regporta_0> of sequential type is unconnected in block <CIAB1>. | |
| xst | WARNING | Xst:2677 - Node <regporta_1> of sequential type is unconnected in block <CIAB1>. | |
| xst | WARNING | Xst:2677 - Node <regporta_2> of sequential type is unconnected in block <CIAB1>. | |
| xst | WARNING | Xst:2677 - Node <regporta_3> of sequential type is unconnected in block <CIAB1>. | |
| xst | WARNING | Xst:2677 - Node <regporta_4> of sequential type is unconnected in block <CIAB1>. | |
| xst | WARNING | Xst:2677 - Node <regporta_5> of sequential type is unconnected in block <CIAB1>. | |
| xst | WARNING | Xst:2677 - Node <mode_0> of sequential type is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <status_1> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <cpu_address_hit> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <freeze> is unconnected in block <km1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <freeze_del> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <status_0> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_1> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_2> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_3> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_4> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_5> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_6> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_7> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <custom_adr_8> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <active> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <after_reset> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <l_int7_ack> is unconnected in block <CART1>. | |
| xst | WARNING | Xst:2677 - Node <icrmask_4> of sequential type is unconnected in block <cnt>. | |
| xst | WARNING | Xst:2677 - Node <icrmask_3> of sequential type is unconnected in block <cnt>. | |
| xst | WARNING | Xst:2677 - Node <mode_0> of sequential type is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_0> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_1> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_2> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_3> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_4> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_5> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_6> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_7> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_8> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_9> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_10> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_11> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_12> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_13> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_14> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_15> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_32> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <scaledin_33> of sequential type is unconnected in block <hybrid_pwm_sd>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_0> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_24> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_25> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_26> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_27> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_28> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_29> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_30> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <_l_addr_31> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <regporta_0> of sequential type is unconnected in block <ciab>. | |
| xst | WARNING | Xst:2677 - Node <regporta_1> of sequential type is unconnected in block <ciab>. | |
| xst | WARNING | Xst:2677 - Node <regporta_2> of sequential type is unconnected in block <ciab>. | |
| xst | WARNING | Xst:2677 - Node <regporta_3> of sequential type is unconnected in block <ciab>. | |
| xst | WARNING | Xst:2677 - Node <regporta_4> of sequential type is unconnected in block <ciab>. | |
| xst | WARNING | Xst:2677 - Node <regporta_5> of sequential type is unconnected in block <ciab>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_0> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_1> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_2> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_3> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_4> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_6> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_7> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_8> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_9> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_10> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_11> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_12> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_13> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_14> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon3_15> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_7> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_8> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_9> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_10> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_11> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_12> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_13> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_14> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:2677 - Node <bplcon2_15> of sequential type is unconnected in block <Denise>. | |
| xst | WARNING | Xst:1426 - The value init of the FF/Latch aron hinder the constant cleaning in the block ActionReplay.
You should achieve better results by setting this init to 1. | |
| xst | WARNING | Xst:1710 - FF/Latch <wr_fifo_status_12> (without init value) has a constant value of 0 in block <floppy>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <wr_fifo_status_13> (without init value) has a constant value of 0 in block <floppy>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <wr_fifo_status_14> (without init value) has a constant value of 0 in block <floppy>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1293 - FF/Latch <aron> has a constant value of 0 in block <ActionReplay>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <int7> (without init value) has a constant value of 0 in block <ActionReplay>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <l_int7_req> (without init value) has a constant value of 0 in block <ActionReplay>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <mode_1> (without init value) has a constant value of 1 in block <ActionReplay>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ram_ovl> (without init value) has a constant value of 0 in block <ActionReplay>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1895 - Due to other FF/Latch trimming, FF/Latch <l_int7> (without init value) has a constant value of 0 in block <ActionReplay>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <status_1> is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <freeze_del> is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <status_0> is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <after_reset> is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <active> is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <cpu_address_hit> is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:1898 - Due to constant pushing, FF/Latch <l_int7_ack> is unconnected in block <ActionReplay>. | |
| xst | WARNING | Xst:1710 - FF/Latch <porta_in2_3> (without init value) has a constant value of 0 in block <ciab>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:2677 - Node <sps6/attach> of sequential type is unconnected in block <sprites>. | |
| xst | WARNING | Xst:2677 - Node <sps4/attach> of sequential type is unconnected in block <sprites>. | |
| xst | WARNING | Xst:2677 - Node <sps2/attach> of sequential type is unconnected in block <sprites>. | |
| xst | WARNING | Xst:2677 - Node <sps0/attach> of sequential type is unconnected in block <sprites>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_29> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_31> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_30> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_26> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_28> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_27> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_25> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_24> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <magic_addr_0> of sequential type is unconnected in block <Mia>. | |
| xst | WARNING | Xst:2677 - Node <verbeam_8> of sequential type is unconnected in block <osd>. | |
| xst | WARNING | Xst:1710 - FF/Latch <reg_address_out_4> (without init value) has a constant value of 0 in block <bpldma_engine>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <reg_address_out_5> (without init value) has a constant value of 0 in block <bpldma_engine>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1710 - FF/Latch <reg_address_out_6> (without init value) has a constant value of 0 in block <bpldma_engine>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1293 - FF/Latch <CIAA1/cnt/icr_4> has a constant value of 0 in block <Minimig1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:1293 - FF/Latch <CIAB1/cnt/icr_3> has a constant value of 0 in block <Minimig1>. This FF/Latch will be trimmed during the optimization process. | |
| xst | WARNING | Xst:2677 - Node <CIAA1/kbd1/km1/freeze> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:2677 - Node <GAYLE1/SECBUF1/empty_wr> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:2677 - Node <USERIO1/osd1/chipset_config_0> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:2677 - Node <USERIO1/osd1/t_chipset_config_0> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:2677 - Node <USERIO1/osd1/floppy_config_1> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:2677 - Node <USERIO1/osd1/scanline_1> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:2677 - Node <CIAA1/cnt/icrmask_4> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:2677 - Node <CIAB1/cnt/icrmask_3> of sequential type is unconnected in block <Minimig1>. | |
| xst | WARNING | Xst:1336 - (*) More than 100% of Device resources are used | |
| map | WARNING | LIT:159 - CLKIN pin of DCM symbol "CLOCK1/cpu_pll" is driven by pin CLKDV of DCM symbol "CLOCK1/dll" (output signal=CLOCK1/dll_c28m). Proper phase relationship to the original clock cannot be guaranteed if the driver is not an IBUF or BUFGMUX. Timing analysis results may not be valid. | |
| map | WARNING | LIT:162 - Only DFS outputs (CLKFX/FX180/CONCUR) of DCM symbol "CLOCK1/cpu_pll" are routed, but CLKFB is not routed. Proper phase relationship of output clocks to CLKIN cannot be guaranteed. | |
| map | WARNING | LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_USERIO1/osd1/clk/CLOCK1/clk_buf" (output signal=USERIO1/osd1/clk) has a mix of clock and non-clock loads. The non-clock loads are:
Pin D of CLOCK1/c3
Pin I0 of CLOCK1/cpu_clk_buf_not00001_INV_0 | |
| map | WARNING | Pack:266 - The function generator PAULA1/pf1/mux_3 failed to merge with F5 multiplexer PAULA1/pf1/mux7_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. | |
| map | WARNING | Pack:266 - The function generator PAULA1/pf1/mux1_3 failed to merge with F5 multiplexer PAULA1/pf1/mux8_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. | |
| map | WARNING | Pack:266 - The function generator PAULA1/pf1/mux1_2_f5_3 failed to merge with F5 multiplexer PAULA1/pf1/mux9_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. | |
| map | WARNING | Pack:266 - The function generator PAULA1/pf1/mux1_2_f5_31 failed to merge with F5 multiplexer PAULA1/pf1/mux10_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. | |
| map | WARNING | Pack:266 - The function generator PAULA1/pf1/mux1_2_f5_32 failed to merge with F5 multiplexer PAULA1/pf1/mux11_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. | |
| map | WARNING | Pack:266 - The function generator PAULA1/pf1/mux1_2_f5_33 failed to merge with F5 multiplexer PAULA1/pf1/mux12_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. | |
| map | WARNING | Pack:266 - The function generator PAULA1/pf1/mux1_2_f5_34 failed to merge with F5 multiplexer PAULA1/pf1/mux13_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. | |
| map | WARNING | PhysDesignRules:372 - Gated clock. Clock net AGNUS1/bpd1/Mrom_reg_address_out_mux00003 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. | |
| map | WARNING | PhysDesignRules:781 - PULLDOWN on an active net. PULLDOWN of comp drv_snd is set but the tri state is not configured. | |
| map | WARNING | PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp pwrled is set but the tri state is not configured. | |
| map | WARNING | PhysDesignRules:812 - Dangling pin <DOA15> on block:<AMBER1/Mram_lbfd.A>:<RAMB16_RAMB16A>. | |
| par | WARNING | Timing:3223 - Timing constraint TS15 = MAXDELAY FROM TIMEGRP "CPU_AS" TO TIMEGRP "CPU_DTACK" 20 ns; ignored during timing analysis. | |
| par | WARNING | Timing:3223 - Timing constraint TS16 = MAXDELAY FROM TIMEGRP "RAMS" TO TIMEGRP "CPU_DTACK" 20 ns; ignored during timing analysis. | |
| par | WARNING | Timing:3223 - Timing constraint TS17 = MAXDELAY FROM TIMEGRP "CPU_DS" TO TIMEGRP "CPU_DTACK" 20 ns; ignored during timing analysis. | |
| par | WARNING | Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <sckbuf1> is placed at site <BUFGMUX1>. The IO component <sck> is placed at site <P90>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <sck.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. | New |
| par | WARNING | Route:455 - CLK Net:USERIO1/osd1/clk may have excessive skew because
0 CLK pins and 2 NON_CLK pins failed to route using a CLK template. | |
| par | WARNING | Route:455 - CLK Net:AGNUS1/bpd1/Mrom_reg_address_out_mux00003 may have excessive skew because
0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. | New |
| trce | WARNING | Timing:3223 - Timing constraint TS15 = MAXDELAY FROM TIMEGRP "CPU_AS" TO TIMEGRP "CPU_DTACK" 20 ns; ignored during timing analysis. | |
| trce | WARNING | Timing:3223 - Timing constraint TS16 = MAXDELAY FROM TIMEGRP "RAMS" TO TIMEGRP "CPU_DTACK" 20 ns; ignored during timing analysis. | |
| trce | WARNING | Timing:3223 - Timing constraint TS17 = MAXDELAY FROM TIMEGRP "CPU_DS" TO TIMEGRP "CPU_DTACK" 20 ns; ignored during timing analysis. | |
| bitgen | WARNING | PhysDesignRules:372 - Gated clock. Clock net AGNUS1/bpd1/Mrom_reg_address_out_mux00003 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. | |
| bitgen | WARNING | PhysDesignRules:781 - PULLDOWN on an active net. PULLDOWN of comp drv_snd is set but the tri state is not configured. | |
| bitgen | WARNING | PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp pwrled is set but the tri state is not configured. | |
| bitgen | WARNING | PhysDesignRules:1095 - General routing resources will be used for the signal CLOCK1/dll_c7m of DCM comp CLOCK1/cpu_pll CLKIN since the driving IOB comp mclk is not located on the same (top or bottom) edge of the device. General routing will cause increased clock delay. To get dedicated clock routing resources, locate both comps on the top edge or the bottom edge of the device. | |
| bitgen | WARNING | PhysDesignRules:812 - Dangling pin <DOA15> on block:<AMBER1/Mram_lbfd.A>:<RAMB16_RAMB16A>. | |
| bitgen | WARNING | Bitgen:200 - CLKFX period 140000 ps is greater than maximum of 41700 ps. | |
| xst | INFO | Xst:1607 - Contents of array <rom_version> may be accessed with an index that does not cover the full array size. | |
| xst | INFO | Xst:2679 - Register <tmcr<4>> in unit <timera> has a constant value of 0 during circuit operation. The register is replaced by logic. | |
| xst | INFO | Xst:2679 - Register <tmcr<4>> in unit <timerb> has a constant value of 0 during circuit operation. The register is replaced by logic. | |
| xst | INFO | Xst:2117 - HDL ADVISOR - Mux Selector <txstate> of Case statement line 576 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <txstate> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization | |
| xst | INFO | Xst:2117 - HDL ADVISOR - Mux Selector <rxstate> of Case statement line 661 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <rxstate> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization | |
| xst | INFO | Xst:1799 - State 11 is never reached in FSM <rxstate>. | |
| xst | INFO | Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. | |
| xst | INFO | Xst:2117 - HDL ADVISOR - Mux Selector <chsel> of Case statement line 541 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
- add an 'INIT' attribute on signal <chsel> (optimization is then done without any risk)
- use the attribute 'signal_encoding user' to avoid onehot optimization
- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization | |
| xst | INFO | Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. | |
| xst | INFO | Xst:2261 - The FF/Latch <wr_fifo_status_12> in Unit <pf1> is equivalent to the following 2 FFs/Latches, which will be removed : <wr_fifo_status_13> <wr_fifo_status_14> | |
| xst | INFO | Xst:3226 - The RAM <Mram_custom> will be implemented as a BLOCK RAM, absorbing the following register(s): | |
| xst | INFO | Xst:3226 - The RAM <Mram_lbfd> will be implemented as a BLOCK RAM, absorbing the following register(s): | |
| xst | INFO | Xst:3226 - The RAM <Mram_lbf> will be implemented as a BLOCK RAM, absorbing the following register(s): | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_bltmod> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_audlch> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_audlcl> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_audpt> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_bplpth> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_bplptl> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_colortable> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): | |
| xst | INFO | Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_tfr> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_colortable> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3226 - The RAM <Mram_osdbuf> will be implemented as a BLOCK RAM, absorbing the following register(s): | |
| xst | INFO | Xst:3044 - The ROM <Mrom_keyrom_mux0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <keyrom>. | |
| xst | INFO | Xst:3225 - The RAM <Mrom_keyrom_mux0000> will be implemented as BLOCK RAM | |
| xst | INFO | Xst:3231 - The small RAM <Mram_sprpth> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. | |
| xst | INFO | Xst:3231 - The small RAM <Mram_sprptl> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_sprpos> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_sprctl> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:3218 - HDL ADVISOR - The RAM <Mram_dmastate_mem> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. | |
| xst | INFO | Xst:2261 - The FF/Latch <porta_in2_3> in Unit <ciab> is equivalent to the following FF/Latch, which will be removed : <porta_in2_5> | |
| xst | INFO | Xst:2261 - The FF/Latch <tx_data_send_7> in Unit <Mia> is equivalent to the following FF/Latch, which will be removed : <tx_data_send_15> | |
| xst | INFO | Xst:2261 - The FF/Latch <reg_address_out_3> in Unit <bpldma_engine> is equivalent to the following FF/Latch, which will be removed : <reg_address_out_7> | |
| xst | INFO | Xst:2261 - The FF/Latch <vsync_del> in Unit <Minimig1> is equivalent to the following FF/Latch, which will be removed : <CIAA1/tick_del> | |
| xst | INFO | Xst:2261 - The FF/Latch <_step_del> in Unit <Minimig1> is equivalent to the following FF/Latch, which will be removed : <PAULA1/pf1/_step_del> | |
| xst | INFO | Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. | |
| map | INFO | LIT:243 - Logical network DENISE1/ham0/Mram_colortable1/SPO has no load. | |
| map | INFO | LIT:395 - The above info message is repeated 130 more times for the following (max. 5 shown):
DENISE1/ham0/Mram_colortable2/SPO,
DENISE1/ham0/Mram_colortable3/SPO,
DENISE1/ham0/Mram_colortable6/SPO,
DENISE1/ham0/Mram_colortable4/SPO,
DENISE1/ham0/Mram_colortable5/SPO
To see the details of these info messages, please use the -detail switch. | |
| map | INFO | MapLib:562 - No environment variables are currently set. | |
| map | INFO | PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp CLOCK1/cpu_pll, consult the device Interactive Data Sheet. | |
| map | INFO | PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp CLOCK1/pll, consult the device Interactive Data Sheet. | |
| par | INFO | Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. | |
| trce | INFO | Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). | |
| trce | INFO | Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. | |
| trce | INFO | Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. | |
| trce | INFO | Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. | |
| trce | INFO | Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. | |
| bitgen | INFO | Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most commonly, bitgen has determined and will use a specific value instead of the generic command-line value of "Auto". Alternately, this message appears if the same option is specified multiple times on the command-line. In this case, the option listed last will be used. | |
| bitgen | INFO | PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp CLOCK1/cpu_pll, consult the device Interactive Data Sheet. | |
| bitgen | INFO | PhysDesignRules:772 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp CLOCK1/pll, consult the device Interactive Data Sheet. | |