Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3
OS Platform: LIN64 Target Device: xc3s400
Project ID (random number) 944d2a7f1f0646c88fdbb6876e744553.2C4EAF0BE4E251D3EAF6C1FB3D04FC8D.2 Target Package: pq208
Registration ID 211975877_1777555008_0_212 Target Speed: -4
Date Generated 2023-06-03T19:54:03 Tool Flow ISE
 
User Environment
OS Name Ubuntu OS Release Ubuntu 22.04.2 LTS
CPU Name Intel(R) Xeon(R) Gold 5122 CPU @ 3.60GHz CPU Speed 3669.503 MHz
CPU Name Intel(R) Xeon(R) Gold 5122 CPU @ 3.60GHz CPU Speed 1199.936 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=38
  • 11-bit adder=1
  • 12-bit subtractor=1
  • 14-bit subtractor=1
  • 15-bit adder=2
  • 15-bit subtractor=1
  • 16-bit adder=2
  • 16-bit subtractor=1
  • 20-bit adder=3
  • 20-bit adder carry in=1
  • 20-bit addsub=2
  • 21-bit adder=1
  • 24-bit adder=2
  • 32-bit adder=1
  • 33-bit adder carry out=2
  • 4-bit adder=4
  • 4-bit adder carry out=3
  • 4-bit subtractor=2
  • 5-bit adder carry out=3
  • 7-bit adder carry out=1
  • 7-bit subtractor=1
  • 8-bit adder=2
  • 8-bit subtractor=1
Comparators=48
  • 10-bit comparator equal=2
  • 11-bit comparator equal=8
  • 11-bit comparator greater=1
  • 11-bit comparator lessequal=1
  • 13-bit comparator equal=1
  • 15-bit comparator greatequal=1
  • 16-bit comparator equal=1
  • 24-bit comparator equal=2
  • 3-bit comparator equal=2
  • 3-bit comparator greater=3
  • 3-bit comparator less=1
  • 32-bit comparator equal=1
  • 32-bit comparator greater=1
  • 4-bit comparator greater=6
  • 5-bit comparator equal=2
  • 5-bit comparator not equal=1
  • 7-bit comparator equal=1
  • 8-bit comparator equal=2
  • 9-bit comparator equal=11
Counters=51
  • 11-bit down counter=1
  • 11-bit up counter=4
  • 12-bit up counter=2
  • 13-bit up counter=2
  • 16-bit down counter=13
  • 16-bit up counter=1
  • 2-bit down counter=1
  • 2-bit up counter=5
  • 20-bit up counter=1
  • 3-bit up counter=6
  • 32-bit down counter=1
  • 32-bit up counter=2
  • 4-bit up counter=5
  • 5-bit up counter=2
  • 6-bit down counter=1
  • 8-bit down counter=1
  • 9-bit up counter=3
FSMs=8 Latches=2
  • 16-bit latch=1
  • 8-bit latch=1
Multiplexers=38
  • 1-bit 4-to-1 multiplexer=34
  • 1-bit 8-to-1 multiplexer=1
  • 12-bit 16-to-1 multiplexer=1
  • 12-bit 4-to-1 multiplexer=1
  • 16-bit 4-to-1 multiplexer=1
Multipliers=4
  • 17x16-bit multiplier=2
  • 8x7-bit multiplier=2
RAMs=24
  • 1024x18-bit dual-port block RAM=1
  • 1024x18-bit single-port block RAM=1
  • 16x12-bit dual-port distributed RAM=1
  • 2048x16-bit dual-port block RAM=1
  • 2048x8-bit dual-port block RAM=1
  • 2048x9-bit single-port block RAM=3
  • 32x12-bit dual-port distributed RAM=1
  • 4096x16-bit dual-port block RAM=1
  • 4x15-bit dual-port distributed RAM=2
  • 4x21-bit single-port distributed RAM=1
  • 4x5-bit dual-port distributed RAM=1
  • 512x16-bit single-port block RAM=1
  • 512x4-bit dual-port block RAM=1
  • 8x1-bit single-port distributed RAM=1
  • 8x12-bit dual-port distributed RAM=1
  • 8x15-bit dual-port distributed RAM=2
  • 8x5-bit dual-port distributed RAM=2
  • 8x8-bit dual-port distributed RAM=1
  • 8x8-bit single-port distributed RAM=1
ROMs=7
  • 16x16-bit ROM=1
  • 32x18-bit ROM=2
  • 4x2-bit ROM=1
  • 4x4-bit ROM=1
  • 4x8-bit ROM=1
  • 6x8-bit ROM=1
Registers=3197
  • Flip-Flops=3197
Shift Registers=6
  • 16-bit dynamic shift register=6
Xors=38
  • 1-bit xor2=36
  • 1-bit xor3=1
  • 6-bit xor2=1
MiscellaneousStatistics
  • AGG_BONDED_IO=140
  • AGG_IO=140
  • AGG_SLICE=3582
  • NUM_4_INPUT_LUT=5690
  • NUM_BONDED_IOB=140
  • NUM_BUFGMUX=4
  • NUM_CYMUX=1055
  • NUM_DCM=3
  • NUM_DP_RAM=262
  • NUM_LUT_RT=331
  • NUM_MULT18X18=8
  • NUM_RAM16=29
  • NUM_RAMB16=14
  • NUM_SHIFT=20
  • NUM_SLICEL=3415
  • NUM_SLICEM=167
  • NUM_SLICE_FF=3737
  • NUM_SLICE_LATCH=20
  • NUM_XOR=834
NetStatistics
  • NumNets_Active=8099
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=246
  • NumNodesOfType_Active_BRAMDUMMY=317
  • NumNodesOfType_Active_CLKPIN=2450
  • NumNodesOfType_Active_CNTRLPIN=3200
  • NumNodesOfType_Active_DOUBLE=24343
  • NumNodesOfType_Active_DUMMY=17585
  • NumNodesOfType_Active_DUMMYBANK=4
  • NumNodesOfType_Active_DUMMYESC=85
  • NumNodesOfType_Active_GLOBAL=460
  • NumNodesOfType_Active_HFULLHEX=782
  • NumNodesOfType_Active_HLONG=214
  • NumNodesOfType_Active_HUNIHEX=4215
  • NumNodesOfType_Active_INPUT=20993
  • NumNodesOfType_Active_IOBOUTPUT=85
  • NumNodesOfType_Active_OMUX=7890
  • NumNodesOfType_Active_OUTPUT=7887
  • NumNodesOfType_Active_PREBXBY=2529
  • NumNodesOfType_Active_VFULLHEX=2484
  • NumNodesOfType_Active_VLONG=399
  • NumNodesOfType_Active_VUNIHEX=2952
  • NumNodesOfType_Vcc_BRAMADDR=1
  • NumNodesOfType_Vcc_BRAMDUMMY=8
  • NumNodesOfType_Vcc_CLKPIN=3
  • NumNodesOfType_Vcc_CNTRLPIN=43
  • NumNodesOfType_Vcc_DUMMY=12
  • NumNodesOfType_Vcc_DUMMYBANK=12
  • NumNodesOfType_Vcc_INPUT=117
  • NumNodesOfType_Vcc_PREBXBY=97
  • NumNodesOfType_Vcc_VCCOUT=122
SiteStatistics
  • IOB-DIFFM=64
  • IOB-DIFFS=62
  • SLICEL-SLICEM=1624
SiteSummary
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • DCM=3
  • DCM_DCM=3
  • IOB=140
  • IOB_INBUF=85
  • IOB_OUTBUF=92
  • IOB_PAD=140
  • MULT18X18=8
  • MULT18X18_BLACKBOX=8
  • RAMB16=14
  • RAMB16_RAMB16=14
  • RAMB16_RAMB16A=14
  • RAMB16_RAMB16B=9
  • SLICEL=3415
  • SLICEL_C1VDD=155
  • SLICEL_C2VDD=138
  • SLICEL_CYMUXF=554
  • SLICEL_CYMUXG=486
  • SLICEL_F=2684
  • SLICEL_F5MUX=381
  • SLICEL_F6MUX=1
  • SLICEL_FFX=1779
  • SLICEL_FFY=1927
  • SLICEL_G=2673
  • SLICEL_GNDF=299
  • SLICEL_GNDG=261
  • SLICEL_XORF=425
  • SLICEL_XORG=409
  • SLICEM=167
  • SLICEM_CYMUXF=9
  • SLICEM_CYMUXG=6
  • SLICEM_F=166
  • SLICEM_FFX=27
  • SLICEM_FFY=24
  • SLICEM_G=167
  • SLICEM_GNDF=9
  • SLICEM_GNDG=6
  • SLICEM_WSGEN=161
 
Configuration Data
BUFGMUX
  • S=[S_INV:3] [S:1]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:3] [S:1]
DCM
  • PSCLK=[PSCLK_INV:3] [PSCLK:0]
  • PSEN=[PSEN_INV:3] [PSEN:0]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:3]
  • RST=[RST:0] [RST_INV:3]
DCM_DCM
  • CLKDV_DIVIDE=[2:2] [4:1]
  • CLKOUT_PHASE_SHIFT=[NONE:3]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[7:3]
  • DFS_FREQUENCY_MODE=[LOW:3]
  • DLL_FREQUENCY_MODE=[LOW:3]
  • DUTY_CYCLE_CORRECTION=[TRUE:3]
  • FACTORY_JF1=[0XC0:3]
  • FACTORY_JF2=[0X80:3]
  • PSCLK=[PSCLK_INV:3] [PSCLK:0]
  • PSEN=[PSEN_INV:3] [PSEN:0]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:3]
  • RST=[RST:0] [RST_INV:3]
  • STARTUP_WAIT=[STARTUP_WAIT:3]
IOB
  • O1=[O1_INV:0] [O1:92]
  • T1=[T1_INV:17] [T1:20]
IOB_IFF1
  • CK=[CK:12] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:12]
  • LATCH_OR_FF=[FF:12]
IOB_OFF1
  • CE=[CE:32] [CE_INV:0]
  • CK=[CK:49] [CK_INV:0]
  • D=[D:48] [D_INV:1]
  • LATCH_OR_FF=[FF:49]
  • OFF1_INIT_ATTR=[INIT0:37] [INIT1:12]
  • OFF1_SR_ATTR=[SRHIGH:12]
  • OFFATTRBOX=[SYNC:12]
  • SR=[SR:11] [SR_INV:1]
IOB_OFF2
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • LATCH_OR_FF=[FF:1]
  • OFF2_INIT_ATTR=[INIT1:1]
  • OFF2_SR_ATTR=[SRHIGH:1]
  • OFFATTRBOX=[SYNC:1]
  • SR=[SR:1] [SR_INV:0]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:92]
  • TRI=[TRI_INV:17] [TRI:20]
IOB_PAD
  • DRIVEATTRBOX=[4:83] [12:8] [24:1]
  • IOATTRBOX=[LVCMOS33:140]
  • PULL=[KEEPER:32] [PULLUP:18]
  • SLEW=[SLOW:90] [FAST:2]
IOB_TFF1
  • CE=[CE:2] [CE_INV:0]
  • CK=[CK:2] [CK_INV:0]
  • D=[D:2] [D_INV:0]
  • LATCH_OR_FF=[FF:2]
  • SR=[SR:2] [SR_INV:0]
  • TFF1_INIT_ATTR=[INIT0:2]
  • TFF1_SR_ATTR=[SRLOW:2]
  • TFFATTRBOX=[SYNC:2]
RAMB16
  • CLKA=[CLKA_INV:3] [CLKA:11]
  • CLKB=[CLKB_INV:0] [CLKB:9]
  • ENA=[ENA_INV:1] [ENA:13]
  • ENB=[ENB_INV:0] [ENB:9]
  • SSRA=[SSRA_INV:0] [SSRA:14]
  • SSRB=[SSRB_INV:0] [SSRB:9]
  • WEA=[WEA:14] [WEA_INV:0]
  • WEB=[WEB:9] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:3] [CLKA:11]
  • ENA=[ENA_INV:1] [ENA:13]
  • PORTA_ATTR=[2048X9:6] [1024X18:3] [4096X4:5]
  • SSRA=[SSRA_INV:0] [SSRA:14]
  • WEA=[WEA:14] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:1] [READ_FIRST:13]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:9]
  • ENB=[ENB_INV:0] [ENB:9]
  • PORTB_ATTR=[2048X9:3] [1024X18:1] [4096X4:5]
  • SSRB=[SSRB_INV:0] [SSRB:9]
  • WEB=[WEB:9] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:9]
SLICEL
  • BX=[BX_INV:20] [BX:1284]
  • BY=[BY:1180] [BY_INV:17]
  • CE=[CE:1697] [CE_INV:77]
  • CIN=[CIN_INV:0] [CIN:473]
  • CLK=[CLK:2221] [CLK_INV:38]
  • SR=[SR:950] [SR_INV:7]
SLICEL_CYMUXF
  • 0=[0:554] [0_INV:0]
  • 1=[1_INV:1] [1:553]
SLICEL_CYMUXG
  • 0=[0:486] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:381] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:1] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:1348] [CE_INV:65]
  • CK=[CK:1755] [CK_INV:24]
  • D=[D:1760] [D_INV:19]
  • FFX_INIT_ATTR=[INIT0:1629] [INIT1:150]
  • FFX_SR_ATTR=[SRLOW:1631] [SRHIGH:148]
  • LATCH_OR_FF=[FF:1763] [LATCH:16]
  • REV=[REV_INV:0] [REV:25]
  • SR=[SR:646] [SR_INV:5]
  • SYNC_ATTR=[ASYNC:1136] [SYNC:643]
SLICEL_FFY
  • CE=[CE:1482] [CE_INV:59]
  • CK=[CK:1896] [CK_INV:31]
  • D=[D:1910] [D_INV:17]
  • FFY_INIT_ATTR=[INIT0:1726] [INIT1:201]
  • FFY_SR_ATTR=[SRLOW:1731] [SRHIGH:196]
  • LATCH_OR_FF=[FF:1923] [LATCH:4]
  • REV=[REV_INV:0] [REV:33]
  • SR=[SR:826] [SR_INV:7]
  • SYNC_ATTR=[ASYNC:1112] [SYNC:815]
SLICEL_XORF
  • 1=[1_INV:1] [1:424]
SLICEM
  • BX=[BX_INV:0] [BX:40]
  • BY=[BY:164] [BY_INV:0]
  • CE=[CE:18] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:6]
  • CLK=[CLK:163] [CLK_INV:1]
  • SR=[SR:155] [SR_INV:6]
SLICEM_CYMUXF
  • 0=[0:9] [0_INV:0]
  • 1=[1_INV:0] [1:9]
SLICEM_CYMUXG
  • 0=[0:6] [0_INV:0]
SLICEM_F
  • DI=[DI:150] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:131] [SHIFT_REG:5]
  • LUT_OR_MEM=[LUT:16] [RAM:150]
SLICEM_FFX
  • CE=[CE:17] [CE_INV:0]
  • CK=[CK:27] [CK_INV:0]
  • D=[D:27] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:27]
  • FFX_SR_ATTR=[SRLOW:27]
  • LATCH_OR_FF=[FF:27]
  • SYNC_ATTR=[ASYNC:27]
SLICEM_FFY
  • CE=[CE:12] [CE_INV:0]
  • CK=[CK:23] [CK_INV:1]
  • D=[D:24] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:24]
  • FFY_SR_ATTR=[SRLOW:24]
  • LATCH_OR_FF=[FF:24]
  • SYNC_ATTR=[ASYNC:24]
SLICEM_G
  • DI=[DI:161] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:131] [SHIFT_REG:15]
  • LUT_OR_MEM=[LUT:6] [RAM:161]
SLICEM_WSGEN
  • CK=[CK:161] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:27]
  • WE=[WE_INV:6] [WE:155]
 
Pin Data
BUFGMUX
  • I0=4
  • I1=1
  • O=4
  • S=4
BUFGMUX_GCLKMUX
  • I0=4
  • I1=1
  • OUT=4
  • S=4
BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKFX=2
  • CLKIN=3
  • LOCKED=1
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
DCM_DCM
  • CLK0=1
  • CLKDV=1
  • CLKFB=1
  • CLKFX=2
  • CLKIN=3
  • LOCKED=1
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
IOB
  • I=85
  • O1=92
  • PAD=140
  • T1=37
IOB_IFF1
  • CK=12
  • D=12
  • Q=12
IOB_INBUF
  • IN=85
  • OUT=85
IOB_OFF1
  • CE=32
  • CK=49
  • D=49
  • Q=49
  • SR=12
IOB_OFF2
  • CE=1
  • CK=1
  • D=1
  • Q=1
  • SR=1
IOB_OUTBUF
  • IN=92
  • OUT=92
  • TRI=37
IOB_PAD
  • PAD=140
IOB_TFF1
  • CE=2
  • CK=2
  • D=2
  • Q=2
  • SR=2
MULT18X18
  • A0=8
  • A1=8
  • A10=8
  • A11=8
  • A12=8
  • A13=8
  • A14=8
  • A15=8
  • A16=8
  • A17=8
  • A2=8
  • A3=8
  • A4=8
  • A5=8
  • A6=8
  • A7=8
  • A8=8
  • A9=8
  • B0=8
  • B1=8
  • B10=8
  • B11=8
  • B12=8
  • B13=8
  • B14=8
  • B15=8
  • B16=8
  • B17=8
  • B2=8
  • B3=8
  • B4=8
  • B5=8
  • B6=8
  • B7=8
  • B8=8
  • B9=8
  • P0=6
  • P1=6
  • P10=6
  • P11=6
  • P12=6
  • P13=6
  • P14=4
  • P15=4
  • P16=6
  • P17=6
  • P18=6
  • P19=6
  • P2=6
  • P20=6
  • P21=6
  • P22=6
  • P23=6
  • P24=6
  • P25=6
  • P26=6
  • P27=6
  • P28=6
  • P29=6
  • P3=6
  • P30=6
  • P31=6
  • P4=6
  • P5=6
  • P6=6
  • P7=6
  • P8=6
  • P9=6
MULT18X18_BLACKBOX
  • A0=8
  • A1=8
  • A10=8
  • A11=8
  • A12=8
  • A13=8
  • A14=8
  • A15=8
  • A16=8
  • A17=8
  • A2=8
  • A3=8
  • A4=8
  • A5=8
  • A6=8
  • A7=8
  • A8=8
  • A9=8
  • B0=8
  • B1=8
  • B10=8
  • B11=8
  • B12=8
  • B13=8
  • B14=8
  • B15=8
  • B16=8
  • B17=8
  • B2=8
  • B3=8
  • B4=8
  • B5=8
  • B6=8
  • B7=8
  • B8=8
  • B9=8
  • P0=6
  • P1=6
  • P10=6
  • P11=6
  • P12=6
  • P13=6
  • P14=4
  • P15=4
  • P16=6
  • P17=6
  • P18=6
  • P19=6
  • P2=6
  • P20=6
  • P21=6
  • P22=6
  • P23=6
  • P24=6
  • P25=6
  • P26=6
  • P27=6
  • P28=6
  • P29=6
  • P3=6
  • P30=6
  • P31=6
  • P4=6
  • P5=6
  • P6=6
  • P7=6
  • P8=6
  • P9=6
RAMB16
  • ADDRA10=14
  • ADDRA11=14
  • ADDRA12=14
  • ADDRA13=14
  • ADDRA2=5
  • ADDRA3=11
  • ADDRA4=14
  • ADDRA5=14
  • ADDRA6=14
  • ADDRA7=14
  • ADDRA8=14
  • ADDRA9=14
  • ADDRB10=9
  • ADDRB11=9
  • ADDRB12=9
  • ADDRB13=9
  • ADDRB2=5
  • ADDRB3=8
  • ADDRB4=9
  • ADDRB5=9
  • ADDRB6=9
  • ADDRB7=9
  • ADDRB8=9
  • ADDRB9=9
  • CLKA=14
  • CLKB=9
  • DIA0=13
  • DIA1=13
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA2=13
  • DIA3=13
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIA8=2
  • DIA9=2
  • DIPA0=8
  • DIPA1=2
  • DOA0=5
  • DOA1=5
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=2
  • DOA15=1
  • DOA2=5
  • DOA3=5
  • DOA4=5
  • DOA5=5
  • DOA6=5
  • DOA7=5
  • DOA8=2
  • DOA9=2
  • DOB0=9
  • DOB1=9
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB2=9
  • DOB3=9
  • DOB4=4
  • DOB5=4
  • DOB6=4
  • DOB7=3
  • DOB8=1
  • DOB9=1
  • DOPA0=3
  • DOPB0=2
  • DOPB1=1
  • ENA=14
  • ENB=9
  • SSRA=14
  • SSRB=9
  • WEA=14
  • WEB=9
RAMB16_RAMB16
  • ADDRA=14
  • ADDRB=9
  • DIA=14
  • DIB=9
  • DOA=14
  • DOB=9
RAMB16_RAMB16A
  • ADDRA=14
  • ADDRA10=14
  • ADDRA11=14
  • ADDRA12=14
  • ADDRA13=14
  • ADDRA2=5
  • ADDRA3=11
  • ADDRA4=14
  • ADDRA5=14
  • ADDRA6=14
  • ADDRA7=14
  • ADDRA8=14
  • ADDRA9=14
  • CLKA=14
  • DIA=14
  • DIA0=13
  • DIA1=13
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA2=13
  • DIA3=13
  • DIA4=8
  • DIA5=8
  • DIA6=8
  • DIA7=8
  • DIA8=2
  • DIA9=2
  • DIPA0=8
  • DIPA1=2
  • DOA=14
  • DOA0=5
  • DOA1=5
  • DOA10=2
  • DOA11=2
  • DOA12=2
  • DOA13=2
  • DOA14=2
  • DOA15=1
  • DOA2=5
  • DOA3=5
  • DOA4=5
  • DOA5=5
  • DOA6=5
  • DOA7=5
  • DOA8=2
  • DOA9=2
  • DOPA0=3
  • ENA=14
  • SSRA=14
  • WEA=14
RAMB16_RAMB16B
  • ADDRB=9
  • ADDRB10=9
  • ADDRB11=9
  • ADDRB12=9
  • ADDRB13=9
  • ADDRB2=5
  • ADDRB3=8
  • ADDRB4=9
  • ADDRB5=9
  • ADDRB6=9
  • ADDRB7=9
  • ADDRB8=9
  • ADDRB9=9
  • CLKB=9
  • DIB=9
  • DOB=9
  • DOB0=9
  • DOB1=9
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB2=9
  • DOB3=9
  • DOB4=4
  • DOB5=4
  • DOB6=4
  • DOB7=3
  • DOB8=1
  • DOB9=1
  • DOPB0=2
  • DOPB1=1
  • ENB=9
  • SSRB=9
  • WEB=9
SLICEL
  • BX=1304
  • BY=1197
  • CE=1774
  • CIN=473
  • CLK=2259
  • COUT=486
  • F1=2670
  • F2=2324
  • F3=2064
  • F4=1244
  • F5=2
  • FXINA=1
  • FXINB=1
  • G1=2656
  • G2=2344
  • G3=2043
  • G4=1272
  • SR=957
  • X=1660
  • XB=30
  • XQ=1779
  • Y=1442
  • YQ=1927
SLICEL_C1VDD
  • 1=155
SLICEL_C2VDD
  • 1=138
SLICEL_CYMUXF
  • 0=554
  • 1=554
  • OUT=554
  • S0=554
SLICEL_CYMUXG
  • 0=486
  • 1=486
  • OUT=486
  • S0=486
SLICEL_F
  • A1=2669
  • A2=2324
  • A3=2064
  • A4=1244
  • D=2684
SLICEL_F5MUX
  • F=381
  • G=381
  • OUT=381
  • S0=381
SLICEL_F6MUX
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
SLICEL_FFX
  • CE=1413
  • CK=1779
  • D=1779
  • Q=1779
  • REV=25
  • SR=651
SLICEL_FFY
  • CE=1541
  • CK=1927
  • D=1927
  • Q=1927
  • REV=33
  • SR=833
SLICEL_G
  • A1=2656
  • A2=2344
  • A3=2043
  • A4=1272
  • D=2673
SLICEL_GNDF
  • 0=299
SLICEL_GNDG
  • 0=261
SLICEL_XORF
  • 0=425
  • 1=425
  • O=425
SLICEL_XORG
  • 0=409
  • 1=409
  • O=409
SLICEM
  • BX=40
  • BY=164
  • CE=18
  • CIN=6
  • CLK=164
  • COUT=6
  • F1=166
  • F2=166
  • F3=162
  • F4=159
  • G1=167
  • G2=167
  • G3=167
  • G4=167
  • SR=161
  • X=150
  • XB=3
  • XQ=27
  • Y=21
  • YQ=24
SLICEM_CYMUXF
  • 0=9
  • 1=9
  • OUT=9
  • S0=9
SLICEM_CYMUXG
  • 0=6
  • 1=6
  • OUT=6
  • S0=6
SLICEM_F
  • A1=166
  • A2=166
  • A3=162
  • A4=159
  • D=166
  • DI=150
  • WF1=145
  • WF2=145
  • WF3=145
  • WF4=145
  • WS=150
SLICEM_FFX
  • CE=17
  • CK=27
  • D=27
  • Q=27
SLICEM_FFY
  • CE=12
  • CK=24
  • D=24
  • Q=24
SLICEM_G
  • A1=167
  • A2=167
  • A3=167
  • A4=167
  • D=36
  • DI=161
  • WG1=146
  • WG2=146
  • WG3=146
  • WG4=146
  • WS=161
SLICEM_GNDF
  • 0=9
SLICEM_GNDG
  • 0=6
SLICEM_WSGEN
  • CK=161
  • WE=161
  • WSF=150
  • WSG=161
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s400-pq208-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s400-pq208-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 28 24 0 0 0 0 0
bitgen 595 595 0 0 0 0 0
map 663 633 0 0 0 0 0
netgen 1 1 0 0 0 0 0
ngc2edif 6 6 0 0 0 0 0
ngdbuild 677 677 0 0 0 0 0
par 630 625 0 0 0 0 0
reportgen 1 1 0 0 0 0 0
trce 624 624 0 0 0 0 0
xst 742 721 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm ( 1 ) /doc/usenglish/isehelp/pn_c_tip_of_day.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserBrowsedStrategyFiles=/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2023-06-03T19:31:33 PROP_intWbtProjectID=2C4EAF0BE4E251D3EAF6C1FB3D04FC8D
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_xstNetlistHierarchy=Rebuilt
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s400 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=pq208 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=21
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_BUFGMUX=1 NGDBUILD_NUM_DCM=3 NGDBUILD_NUM_FD=497
NGDBUILD_NUM_FDC=12 NGDBUILD_NUM_FDCE=42 NGDBUILD_NUM_FDCE_1=1 NGDBUILD_NUM_FDE=1677
NGDBUILD_NUM_FDE_1=2 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_FDPE=11 NGDBUILD_NUM_FDR=120
NGDBUILD_NUM_FDRE=945 NGDBUILD_NUM_FDRS=32 NGDBUILD_NUM_FDRSE=26 NGDBUILD_NUM_FDR_1=1
NGDBUILD_NUM_FDS=37 NGDBUILD_NUM_FDSE=290 NGDBUILD_NUM_FDS_1=8 NGDBUILD_NUM_FD_1=35
NGDBUILD_NUM_GND=65 NGDBUILD_NUM_IBUF=46 NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=378
NGDBUILD_NUM_IOBUF=37 NGDBUILD_NUM_LD=4 NGDBUILD_NUM_LD_1=16 NGDBUILD_NUM_LUT1=314
NGDBUILD_NUM_LUT2=523 NGDBUILD_NUM_LUT2_D=7 NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=1592
NGDBUILD_NUM_LUT3_D=24 NGDBUILD_NUM_LUT3_L=10 NGDBUILD_NUM_LUT4=2374 NGDBUILD_NUM_LUT4_D=77
NGDBUILD_NUM_LUT4_L=81 NGDBUILD_NUM_MULT18X18=8 NGDBUILD_NUM_MUXCY=1055 NGDBUILD_NUM_MUXF5=381
NGDBUILD_NUM_MUXF6=1 NGDBUILD_NUM_OBUF=55 NGDBUILD_NUM_RAM16X1D=131 NGDBUILD_NUM_RAM16X1S=29
NGDBUILD_NUM_SRL16=8 NGDBUILD_NUM_SRLC16E=13 NGDBUILD_NUM_VCC=55 NGDBUILD_NUM_XORCY=834
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3 NGDBUILD_NUM_BUFGMUX=1 NGDBUILD_NUM_DCM=3 NGDBUILD_NUM_FD=497
NGDBUILD_NUM_FDC=12 NGDBUILD_NUM_FDCE=42 NGDBUILD_NUM_FDCE_1=1 NGDBUILD_NUM_FDE=1677
NGDBUILD_NUM_FDE_1=2 NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_FDPE=11 NGDBUILD_NUM_FDR=120
NGDBUILD_NUM_FDRE=945 NGDBUILD_NUM_FDRS=32 NGDBUILD_NUM_FDRSE=26 NGDBUILD_NUM_FDR_1=1
NGDBUILD_NUM_FDS=37 NGDBUILD_NUM_FDSE=290 NGDBUILD_NUM_FDS_1=8 NGDBUILD_NUM_FD_1=35
NGDBUILD_NUM_GND=65 NGDBUILD_NUM_IBUF=83 NGDBUILD_NUM_IBUFG=2 NGDBUILD_NUM_INV=378
NGDBUILD_NUM_KEEPER=32 NGDBUILD_NUM_LD=4 NGDBUILD_NUM_LD_1=16 NGDBUILD_NUM_LUT1=314
NGDBUILD_NUM_LUT2=523 NGDBUILD_NUM_LUT2_D=7 NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=1592
NGDBUILD_NUM_LUT3_D=24 NGDBUILD_NUM_LUT3_L=10 NGDBUILD_NUM_LUT4=2374 NGDBUILD_NUM_LUT4_D=77
NGDBUILD_NUM_LUT4_L=81 NGDBUILD_NUM_MULT18X18=8 NGDBUILD_NUM_MUXCY=1055 NGDBUILD_NUM_MUXF5=381
NGDBUILD_NUM_MUXF6=1 NGDBUILD_NUM_OBUF=55 NGDBUILD_NUM_OBUFT=37 NGDBUILD_NUM_PULLUP=18
NGDBUILD_NUM_RAM16X1S=29 NGDBUILD_NUM_RAMB16_S18=2 NGDBUILD_NUM_RAMB16_S18_S18=1 NGDBUILD_NUM_RAMB16_S4_S4=5
NGDBUILD_NUM_RAMB16_S9=3 NGDBUILD_NUM_RAMB16_S9_S9=3 NGDBUILD_NUM_SRLC16E=21 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=55 NGDBUILD_NUM_XORCY=834
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s400-4-pq208 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=Rebuilt -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=8
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5