Minimig1 Project Status (05/10/2023 - 15:57:14)
Project File: Minimig.xise Parser Errors: No Errors
Module Name: Minimig1 Implementation State: Programming File Generated
Target Device: xc3s400-5pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
326 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 3,762 7,168 52%  
    Number used as Flip Flops 3,742      
    Number used as Latches 20      
Number of 4 input LUTs 5,302 7,168 73%  
Number of occupied Slices 3,582 3,584 99%  
    Number of Slices containing only related logic 3,582 3,582 100%  
    Number of Slices containing unrelated logic 0 3,582 0%  
Total Number of 4 input LUTs 5,633 7,168 78%  
    Number used as logic 4,991      
    Number used as a route-thru 331      
    Number used as 16x1 RAMs 29      
    Number used for Dual Port RAMs 262      
    Number used as Shift registers 20      
Number of bonded IOBs 140 141 99%  
Number of RAMB16s 14 16 87%  
Number of MULT18X18s 8 16 50%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 3 4 75%  
Average Fanout of Non-Clock Nets 3.25      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed May 10 15:56:12 20230299 Warnings (0 new)55 Infos (0 new)
Translation ReportCurrentWed May 10 15:56:18 2023000
Map ReportCurrentWed May 10 15:56:26 2023013 Warnings (0 new)5 Infos (0 new)
Place and Route ReportCurrentWed May 10 15:56:57 202307 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed May 10 15:57:01 202303 Warnings (0 new)5 Infos (0 new)
Bitgen ReportCurrentWed May 10 15:57:12 202304 Warnings (0 new)3 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSat Jan 21 00:26:27 2023
WebTalk ReportCurrentWed May 10 15:57:13 2023
WebTalk Log FileCurrentWed May 10 15:57:14 2023

Date Generated: 05/10/2023 - 15:57:14