Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Timing Performance |
PROP_LastAppliedStrategy=Performance with IOB Packing;/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_performance_with_iobpacking.xds |
PROP_ManualCompileOrderImp=false |
PROP_ProjectDescription=My atempt to change timings. :) |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthOptEffort=High |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_performance_with_iobpacking.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2022-01-20T12:32:14 |
PROP_intWbtProjectID=DD4E74916F3924C4D81E2ABD48033DBF |
PROP_intWbtProjectIteration=209 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxMapPackRegInto=For Inputs and Outputs |
PROP_xilxMapTimingDrivenPacking=true |
PROP_xilxPARplacerEffortLevel=High |
PROP_xilxPARrouterEffortLevel=High |
PROP_xilxSynthRegBalancing=Yes |
PROP_xstPackIORegister=Yes |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_MapPlacerCostTable=50 |
PROP_DevDevice=xc3s400 |
PROP_DevFamilyPMName=spartan3 |
PROP_MapExtraEffort=Normal |
PROP_xilxPARextraEffortLevel=Normal |
PROP_xilxPARplacerCostTable=50 |
PROP_DevPackage=pq208 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
FILE_UCF=1 |
FILE_VERILOG=20 |