Minimig1 Project Status (01/24/2023 - 13:50:43)
Project File: Minimig.xise Parser Errors: No Errors
Module Name: Minimig1 Implementation State: Programming File Generated
Target Device: xc3s400-5pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
304 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 3,753 7,168 52%  
    Number used as Flip Flops 3,733      
    Number used as Latches 20      
Number of 4 input LUTs 5,322 7,168 74%  
Number of occupied Slices 3,582 3,584 99%  
    Number of Slices containing only related logic 3,582 3,582 100%  
    Number of Slices containing unrelated logic 0 3,582 0%  
Total Number of 4 input LUTs 5,652 7,168 78%  
    Number used as logic 5,011      
    Number used as a route-thru 330      
    Number used as 16x1 RAMs 29      
    Number used for Dual Port RAMs 262      
    Number used as Shift registers 20      
Number of bonded IOBs 139 141 98%  
Number of RAMB16s 13 16 81%  
Number of MULT18X18s 8 16 50%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 3 4 75%  
Average Fanout of Non-Clock Nets 3.24      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Feb 17 23:15:43 20230274 Warnings (0 new)41 Infos (0 new)
Translation ReportCurrentFri Feb 17 23:15:51 2023000
Map ReportCurrentFri Feb 17 23:16:01 2023014 Warnings (0 new)5 Infos (0 new)
Place and Route ReportCurrentFri Feb 17 23:16:38 202307 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Feb 17 23:16:43 202303 Warnings (0 new)5 Infos (0 new)
Bitgen ReportCurrentFri Feb 17 23:16:59 202306 Warnings (0 new)3 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSat Jan 21 00:26:27 2023
WebTalk ReportCurrentFri Feb 17 23:17:00 2023
WebTalk Log FileCurrentFri Feb 17 23:17:00 2023

Date Generated: 02/19/2023 - 00:27:30