Minimig1 Project Status (02/19/2023 - 00:09:22)
Project File: Minimig.xise Parser Errors: No Errors
Module Name: Minimig1 Implementation State: Synthesized
Target Device: xc3s400-4pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
269 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed May 3 19:35:44 20230269 Warnings (0 new)39 Infos (0 new)
Translation ReportOut of DateTue Apr 18 21:53:30 2023000
Map ReportOut of DateTue Apr 18 21:54:13 202303884 Warnings (0 new)8 Infos (0 new)
Place and Route ReportOut of DateTue Mar 7 00:13:19 202304 Warnings (1 new)0
Power Report     
Post-PAR Static Timing ReportOut of DateTue Mar 7 00:13:23 2023005 Infos (0 new)
Bitgen ReportOut of DateTue Mar 7 00:13:35 202305 Warnings (0 new)3 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateTue Mar 7 00:13:36 2023
WebTalk Log FileOut of DateTue Mar 7 00:13:37 2023

Date Generated: 05/03/2023 - 19:55:25