Minimig1 Project Status (05/10/2023 - 14:12:18)
Project File: Minimig_autoconfig_git.xise Parser Errors: No Errors
Module Name: Minimig1 Implementation State: Programming File Generated
Target Device: xc3s400-4pq208
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
277 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 1 Failing Constraint
Environment: System Settings
  • Final Timing Score:
22289  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 3,757 7,168 52%  
    Number used as Flip Flops 3,737      
    Number used as Latches 20      
Number of 4 input LUTs 5,347 7,168 74%  
Number of occupied Slices 3,582 3,584 99%  
    Number of Slices containing only related logic 3,582 3,582 100%  
    Number of Slices containing unrelated logic 0 3,582 0%  
Total Number of 4 input LUTs 5,678 7,168 79%  
    Number used as logic 5,036      
    Number used as a route-thru 331      
    Number used as 16x1 RAMs 29      
    Number used for Dual Port RAMs 262      
    Number used as Shift registers 20      
Number of bonded IOBs 140 141 99%  
Number of RAMB16s 14 16 87%  
Number of MULT18X18s 8 16 50%  
Number of BUFGMUXs 4 8 50%  
Number of DCMs 3 4 75%  
Average Fanout of Non-Clock Nets 3.24      
 
Performance Summary [-]
Final Timing Score: 22289 (Setup: 22289, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 1 Failing Constraint    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed May 10 14:09:34 20230255 Warnings (0 new)48 Infos (0 new)
Translation ReportCurrentWed May 10 14:09:39 2023000
Map ReportCurrentWed May 10 14:09:48 2023013 Warnings (0 new)5 Infos (0 new)
Place and Route ReportCurrentWed May 10 14:11:59 202305 Warnings (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentWed May 10 14:12:03 2023005 Infos (0 new)
Bitgen ReportCurrentWed May 10 14:12:16 202304 Warnings (0 new)3 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed May 10 14:12:17 2023
WebTalk Log FileCurrentWed May 10 14:12:18 2023

Date Generated: 05/10/2023 - 14:12:18